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2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT7521
Rev. 1.0.8
2
FT7521
—
Re
set
Ti
mer
with
Fi
x
ed
De
lay
and
Rese
t
Pulse
Recommended Application Diagram
Open-Drain Output
Digital Logic &
Counter
Voltage
Reference
/SR0
DSR
/RST1
50k
RPU
VCC
TEST
10k
Baseband or PMIC
100nF
Oscillator
Figure 2.
Recommended Application Diagram
Pin Configuration
Figure 3.
Pad Assignments (Top-Through View)
Pin Definitions
Pin #
Name
Description
Normal Operation
Zero-Second Factory-Test Mode
1
/RST1
Open-drain output, active LOW
2
GND
3
/SR0
Reset Input with Integrated pull-up, active LOW
Reset input with integrated pull-up, active LOW
4
VCC
Power supply
5
DSR
Delay selection input; tie to GND during normal
operation.
(1)
Delay selection input. Pull HIGH to enable zero-
second delay for factory test.
6
TEST
Used for device testing; tie to GND during
normal operation.
Used for device testing; tie to GND during
normal operation.
Note:
1.
This pin must always be tied to either GND or VCC. It must not float.
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